1. Field of the Invention
The present invention generally relates to an oscillation circuit which is used in microcomputers, IC cards and the like. More particularly, the invention is concerned with an oscillation circuit which can operate stably over an extended range of operating voltages. With the term "microcomputer", it is contemplated to mean small computer system and cover small business or office computers and personal computers. Further, the "IC card" covers those typified by chip card, intelligent card, smart card and the like.
2. Description of Related Art
Heretofore, the microcomputers and the devices mentioned above have been designed to operate with a single operating voltage usually standardized to 5 volts. In that case, it is sufficient for the oscillation circuit incorporated in the microcomputers to operate with a single operating voltage. In recent years, however, there increasingly arose a demand for battery-driven microcomputers such as notebook-size personal computers, handy-type terminals and the like, which in turn requires oscillation circuits which are capable of operating at various voltages within a wide voltage range. However, broadening of the operating voltage range of the oscillation circuit is accompanied with problems to be Solved, which will be explained below in conjunction with a typical one of the conventional oscillation circuits.
FIG. 6 is a diagram showing an oscillation circuit known heretofore which is used in a charge pump for internally generating voltage signals to be supplied to a UART (Universal Asynchronous Receiver/Transmitter), an EEPROM (Electrically Erasable and Programmable Read-Only Memory) and others incorporated in microcomputers, IC cards and other elements. Referring to FIG. 6, the oscillation circuit includes a NAND circuit 1 having first and second input terminals, a first inverter 2 having an input terminal to which the output terminal of the NAND circuit 1 is connected and an output terminal connected to one end of a first capacitor 4 via a first resistor 3. The other end of the first capacitor 4 is grounded. A junction (i.e., node of connection) between the first resistor 3 and the first capacitor 4 is connected to an input terminal of a second inverter 5 which has an output terminal connected to one end of a second capacitor 7 via a second resistor 6. The other end of the second capacitor 7 is grounded. A junction between the second resistor 6 and the second capacitor 7 is connected to an output terminal 8 of the oscillation circuit on one hand and connected to the second input terminal of the NAND circuit 1 on the other hand. The first input terminal of the NAND circuit 1 is connected to an input terminal 9 of the oscillation circuit. Parenthetically, the first inverter 2, the first resistor 3 and the first capacitor 4 constitute one circuit unit 10a, while the another circuit unit 10b is constituted by the second inverter 5, the second resistor 6 and the second capacitor 7. Of course, more than two circuit units of the same configuration as the circuit units 10a and 10b may be connected in cascade, if desired.
As a trigger signal for triggering operation of the oscillation circuit, an enable signal EN is supplied to the first input terminal of the NAND circuit 1 from a CPU (Central Processing Unit) or the like incorporated in the microcomputer or IC card. When the enable signal EN is fixed to a low level (L), the output of the NAND circuit 1 takes on a high level (H). This high-level output of the NAND circuit 1 is transmitted to the output terminal 8 via a series connection of the first inverter 2 and the first resistor 3 as well as the second inverter 5 and the second resistor 6 connected in series. Thus, an output signal OUT of high level (H) appears at the output terminal 8 of the oscillation circuit. This output signal OUT is fed back to the second input terminal of the NAND circuit 1. However, because the enable signal EN applied to the first input terminal of the NAND circuit 1 is fixed at the low level, the output of the NAND circuit 1 remains constantly at the high level.
When the enable signal EN is changed from the low level to the high level, the output of the NAND circuit 1 changes from the high to the low level, which results in change of the output signal OUT at the output terminal 8 to the low level from the high level. At this time, the feedback signal applied to the second input terminal of the NAND circuit 1 becomes low. Consequently, the output of the NAND circuit 1 becomes high with the result that the level of the output signal OUT at the output terminal 8 is also high. Through repetition of the operation described above, there takes place oscillation in the oscillation circuit, wherein the oscillation frequency is determined by a time constant which in turn is determined by the values of the first resistor 3, the second resistor 6, the first capacitor 4 and the second capacitor 7. FIG. 7 shows a waveform of the oscillation signal output from the output terminal 8. The curvilinear rising edges and falling edges of the pulse-like waves depend on the time constant mentioned above. In order to allow the periodic signal generated by the oscillation circuit to be utilized as a clock signal, the signal will have to be shaped by a suitable shaper circuit.
The prior art oscillation circuit described above suffers a problem that because each of the circuit units 10a and 10b includes a single inverter (2 or 5), the oscillation frequency characteristics of the oscillation circuit depend on the driving capability of the first inverter 2 or the second inverter 5 to a great extent. With the phrase "driving capability" used herein, it is contemplated to mean a parameter indicating magnitude of a current which can be driven by the inverter. Since the inverter is constituted by an N-channel transistor and a P-channel transistor, the driving capability of the former is determined by that of the latter.
As mentioned previously, in the prior art oscillation circuit, the frequency of oscillation depends on a time constant (a delay factor) which in turn is determined by values of the resistor (3, 6) and the capacitor (4, 7) connected to the inverter (2, 5). Besides, the transistor itself which constitutes the inverter (2, 5) has a resistance component (internal resistance) which bears such a relation to the driving capability of the inverter (2, 5) that the internal resistance assumes a smaller value as the driving capability becomes greater and vice versa.
For the reasons mentioned above, if the driving capability of the inverters 2 and 5 is low when a wide range of operating voltage ranging from about 2.7 to 5.5 volts is to be ensured for the oscillation circuit, the influence of the internal resistance of the transistors constituting the inverter becomes significant and broadens the waveform of the output signal of the oscillation circuit (i.e., the time taken for the rising and falling of the pulse is increased), which results in that the oscillation frequency deviates from a preset value to a lower frequency. On the other hand, when the driving capability of the inverters 2 and 5 are enhanced, the broadening of the waveform (and hence deviation from the preset frequency) can certainly be mitigated. However, in that case, power consumption of the inverters and hence the oscillation circuit increases, giving rise to a problem.